What Is the Slow Part of Chip Design?

Rene Haas says AI is already strong at the slow part of chip design at Arm, which is verification, validation, debug, and documentation rather than drawing the architecture. A design takes 24 to 36 months depending on complexity. RTL generation and mapping the architecture are not the largest share of that time.

Daily use covers probably 80 to 90 percent of engineers at Arm. Turning the tools off would feel like the 1990s, with the internet only between the hours of two and four and a library down the hall for everything after that. RTL generation and best-in-class physical design are still immature because models train on public material while a lot of the information stays proprietary. Work with model makers is underway to close the gap.

Arm's core IP business holds a very rich portfolio: the IP itself, the documentation, the test benches, and the explanation of how to build the IP. IP with no documentation is unusable and untestable. Untestable IP is untrainable, and untrainable IP is not usable for AI. The business model is built to take advantage of the tools as they get better.