How Small Can Hybrid Bonding Get?

Tyler Osborne says hybrid bonding still has a long runway: first-level interconnect was a 130 to 150 micrometer pitch fifteen years ago, Intel ships 25 micrometers in high volume on Foveros, the lab is already under 10 micrometers, and a paper this year showed reliability data at a 0.45 micron pitch.

Intel bonds wafers in two ways. Wafer-to-wafer, already dominant in CMOS image sensors, stacks a full wafer on another wafer. That needs dies that match one to one, including which dies sorted good. If the good and bad dies do not line up, good chips are bonded to bad ones and that yield is lost. Chip-to-wafer lets Intel test dies first and bond a known-good die only onto a known-good spot. Osborne expects Intel to do both. Chip-to-wafer makes more sense for logic bonded to logic, and the choice follows the customer and the architecture.

The last wiring layers inside a chip are typically about one micron down to half a micron. Push the bond pitch to 0.5 micron or below and those layers can connect straight from one chip to the other, with less total resistance between the two transistor layers.