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Why Can't Chip Fabs 10x Wafer Output for AI? · Dwarkesh Podcast

Dwarkesh Podcast

What will computer chips look like in 2045?

I spent two days touring Intel’s most advanced fab and talking to its technical leadership to understand what the chips of the future will look like. A lot of what's coming next – gate-all-around transistors, backside power, CFET, hybrid bonding – is hard to follow without actually seeing it, so we made all the awesome animated explainers that I wish I had…

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Notes

Why Did Intel's 10 Nanometer Node Slip? at 3:22

Chris Auth says Intel's 10 nanometer node slipped because the targets were more aggressive than historical scaling, and extreme ultraviolet lithography was… Full answer
What Is a Gate-all-around Transistor? at 6:55

Dwarkesh Patel says a gate-all-around transistor slices the silicon channel into thin ribbons and wraps the gate completely around each ribbon, so the gate… Full answer
Why Does high-NA EUV Pay Off for Intel and Not TSMC? at 13:17

Chris Auth says high-NA extreme ultraviolet lithography pays off for Intel, and not yet for TSMC, because Intel's backside power relaxes the front-side wiring… Full answer
What Will Computer Chips Look Like in 2045? at 19:20

Chris Auth says chips in 2045 can be exotic three-dimensional structures, with transistors floating in the interconnect and stacked the way memory already… Full answer
Why Can't Logic Chips Stack Like Memory? at 21:49

Chris Auth says logic chips cannot stack like memory because logic uses more power and the heat has no clear way out. Full answer
What Is an Intel Hotbox? at 28:35

Kevin Fischer says an Intel hotbox is a priority grade for one lot, a block of silicon, so that lot races through the fab ahead of everything else. Full answer
Why Would Ruthenium Replace Copper Chip Wires? at 29:34

Jack Kavalieros says ruthenium can replace copper on the tightest chip wires because ruthenium can be etched and does not need the liner copper requires, so… Full answer
How Small Can Hybrid Bonding Get? at 43:53

Tyler Osborne says hybrid bonding still has a long runway: first-level interconnect was a 130 to 150 micrometer pitch fifteen years ago, Intel ships 25… Full answer
Why Can't Chip Fabs 10x Wafer Output for AI? at 48:10

Pushkar Ranade, Intel's CTO, says the world's chip tools can about double leading-edge wafer output, not multiply it by ten, even if AI labs want far more… Full answer
How Does Intel Plan to Catch Up to TSMC? at 53:14

Pushkar Ranade says Intel's catch-up with TSMC is a scale problem, not a missing generation of transistor technology. Full answer
Why Will Intel Buy More Chipmaking Tools? at 1:07:43

Pushkar Ranade says Intel will invest more in chipmaking tools, and would have bought more a year ago if today's AI demand had been clear then. Full answer

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